Q$2.$ Basic MIPS $5-$stage pipeline

Consider the following MIPS code:

Suppose we have the simple MIPS $5-$stage pipeline from Appendix C in the book $($i$.$e$.,$ every instruction

must go through all $5$ stages$).$

$($a$)$ Fill in the two pipeline timing charts that show the execution of the instructions. For the first

chart, assume that no forwarding is available, except the in$-$cycle forwarding $-$ i$.$e$.,$ the register

file will be written in the first half of a clock cycle and be read in the second half of the clock

cycle. For the second chart, assume that forwarding is available in the pipeline.

Without forwarding