Q$2.$ Use the following code fragment:

Loop: ld $x2,0(x1)$

ld $x4,0(x3)$

add $x5,x2,x4$

sd $x5,0(x3)$

addi $x1,x1,8$

addi $x3,x3,8$

sub $x7,x6,x3$

bnez $x7,$ Loop

or $,x10,x8,x9$

Assume that the initial value of $x6$ is $x3+280.$

Assume early evaluation of branch instruction, i$.$e$.,$ the branch outcome $($whether the condition is

true or false and where is the next instruction$)$ is known after the Decode stage., but the branch

instruction will still go through all the five pipeline stages.

For both Q$2.$a and Q$2.$b$,$ assume that the branch is handled by predicting it as not$-$taken, i$.$e$.$ the

next instruction in program sequence $($the or instruction$)$ is fetched, which is a wrong instruction

except for the last iteration and will be flushed after the branch outcome is known.

a$.[40$ pts$]$ Show the timing of this instruction sequence for the $5-$stage RISC pipeline without

any forwarding hardware but assuming that a register read and a write in the same clock

cycle "forwards" through the register file, as between the "add" and $"$or$"$ shown in Figure

C$\mathrm{.}5.$ Use a pipeline timing chart like that in Figure C$\mathrm{.}8.$ If all memory references take $1$

cycle $($in the MEM stage$),$ how many cycles does this loop take to execute?

b$.[40$ pts$]$ Show the timing of this instruction sequence for the $5-$stage RISC pipeline with

full forwarding hardware. Use a pipeline timing chart like that shown in Figure C$\mathrm{.}8.$ If all

memory references take $1$ cycle $($in the MEM stage$),$ how many cycles does this loop take

to execute?