Use the following code fragment: Loop:

ld x$2,0($x$1)$

ld x$4,0($x$3)$

add x$5,$ x$2,$ x$4$

sd x$5,0($x$3)$

addi x$1,$ x$1,8$

addi x$3,$ x$3,8$

sub x$7,$ x$6,$ x$3$

bnez x$7,$ Loop

or x$10,$ x$8,$ x$9$

Assume that the initial value of x$6$ is x$3+280.$ Assume early evaluation of branch instruction, i$.$e$.,$ the branch outcome $($whether the condition is true or false and where is the next instruction$)$ is known after the Decode stage., but the branch instruction will still go through all the five pipeline stages. For both Q$2.$a and Q$2.$b$,$ assume that the branch is handled by predicting it as not$-$taken, i$.$e$.$ the next instruction in program sequence $($the or instruction$)$ is fetched, which is a wrong instruction except for the last iteration and will be flushed after the branch outcome is known.

$2$a Show the timing of this instruction sequence for the $5-$stage RISC pipeline without any forwarding hardware but assuming that a register read and a write in the same clock cycle $$forwards$$ through the register file, as between the $$add$$ and $$or$$ Use a pipeline timing chart. If all memory references take $1$ cycle $($in the MEM stage$),$ how many cycles does this loop take to execute

$2$b Show the timing of this instruction sequence for the $5-$stage RISC pipeline with

full forwarding hardware.how many cycles does this loop take

to execute