Q2.Consider the single cycle CPU with the circuit as given on the attached sheet. The following are the latencies of each component: Instruction memory Add 4 unit Mux 300 ps 40 ps 20 ps 150 ps Registers Sign Extend Main Control ALU Control ALU Data Memory shift Left2 (both) AND2 10 ps 120 ps 60 pS 140 ps 350 pS 5 ps 10 0S Assuming "lw" is the instruction being executed, do a componentwise analysis and determine the clock cycle time Q2.Consider the single cycle CPU with the circuit as given on the attached sheet. The following are the latencies of each component: Instruction memory Add 4 unit Mux 300 ps 40 ps 20 ps 150 ps Registers Sign Extend Main Control ALU Control ALU Data Memory shift Left2 (both) AND2 10 ps 120 ps 60 pS 140 ps 350 pS 5 ps 10 0S Assuming "lw" is the instruction being executed, do a componentwise analysis and determine the clock cycle time