Question: question 1 A-Using Quartus II, create a Verilog file for the 4-bit full-adder and simulate it. B- Using Quartus II, create a Verilog file for

question 1

A-Using Quartus II, create a Verilog file for the 4-bit full-adder and simulate it. B- Using Quartus II, create a Verilog file for a 4-bit comparator and simulate it. C- Using Quartus II, create a Verilog file for a 2 by 1 mux and simulate it.

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