Question $1$: Bitwise XOR Instruction

Instruction: xor R$0,$ R$1,$ R$2$

This instruction performs a bitwise XOR operation between the values in registers R$1$ and R$2$ and stores the result in register R$0.$

Group of answer choices:

a$)$ MUX$1$: src$1$ reg $($data$),$ MUX$2$: immd, MUX$3$: NPC$,$ MUX$4$: Mem $($data$)$

b$)$ MUX$1$: src$1$ reg $($data$),$ MUX$2$: immd, MUX$3$: NPC$,$ MUX$4$: none

c$)$ MUX$1$: src$1$ reg $($data$),$ MUX$2$: src$2$ reg $($data$),$ MUX$3$: NPC$,$ MUX$4$: ALU$\_$Out

d$)$ MUX$1$: NPC$,$ MUX$2$: immd, MUX$3$: NPC$,$ MUX$4$: none

e$)$ MUX$1$: NPC$,$ MUX$2$: immd, MUX$3$: ALU$\_$Out, MUX$4$: none

Question $2$: Conditional Branch Instruction

Instruction: jnz $100($assume the branch is not taken$)$

This instruction performs a conditional branch to address $100$ if the zero flag is not set.

Group of answer choices:

a$)$ MUX$1$: src$1$ reg $($data$),$ MUX$2$: immd, MUX$3$: NPC$,$ MUX$4$: Mem $($data$)$

b$)$ MUX$1$: src$1$ reg $($data$),$ MUX$2$: immd, MUX$3$: NPC$,$ MUX$4$: none

c$)$ MUX$1$: src$1$ reg $($data$),$ MUX$2$: src$2$ reg $($data$),$ MUX$3$: NPC$,$ MUX$4$: ALU$\_$Out

d$)$ MUX$1$: NPC$,$ MUX$2$: immd, MUX$3$: NPC$,$ MUX$4$: none

e$)$ MUX$1$: NPC$,$ MUX$2$: immd, MUX$3$: ALU$\_$Out, MUX$4$: none

Question $3$: Unconditional Branch Instruction

Instruction: jmp $100($unconditional branches are always taken$)$

This instruction performs an unconditional branch to address $100.$

Group of answer choices:

a$)$ MUX$1$: src$1$ reg $($data$),$ MUX$2$: immd, MUX$3$: NPC$,$ MUX$4$: Mem $($data$)$

b$)$ MUX$1$: src$1$ reg $($data$),$ MUX$2$: immd, MUX$3$: NPC$,$ MUX$4$: none

c$)$ MUX$1$: src$1$ reg $($data$),$ MUX$2$: src$2$ reg $($data$),$ MUX$3$: NPC$,$ MUX$4$: ALU$\_$Out

d$)$ MUX$1$: NPC$,$ MUX$2$: immd, MUX$3$: NPC$,$ MUX$4$: none

e$)$ MUX$1$: NPC$,$ MUX$2$: immd, MUX$3$: ALU$\_$Out, MUX$4$: none

Question $4$: Multiplexer $2$ Inputs

Question: Please give the two inputs of each multiplexer $2.$

Group of answer choices:

a$)$ MUX$2$: Input $1$: NPC$,$ Input $2$: Src$1$ Reg $($data$)$

b$)$ MUX$2$: Input $1$: Src$2$ Reg $($data$),$ Input $2$: immd $($immediate value$)$

c$)$ MUX$2$: Input $1$: NPC$,$ Input $2$: ALU Out$2$

d$)$ MUX$2$: Input $1$: ALU Out, Input $2$: Mem $($data$)$