Question \#2 (Memory Hierarchy) (20 points) Sketch the memory hierarchy found in the ARM Cortex A77 used in Qualcomm's Snapdragon 865 processor. The Cortex-A 77 has a private L1I, L1D, and L2 cache with the following parameters. L1I and L1D are virtually indexed, physically tagged. All caches use pseudo-LRU cache (tree-based) replacement policy. Assume page sizes are 16 KB. For each hardware structure, indicate all relevant fields (e.g., tags, valid flags, and others) and their length in bits. Use Figure 2.25 from the textbook as a template for your answer. L1I Cache - 64KiB,4-way set associative - 64-byte cache lines - Write-back L1D Cache - 64KiB,4-way set associative - 64-byte cache lines - Write-back L2 Cache - 512KiB - 8-way set associative - Strictly inclusive of the L1 data cache \& non-inclusive of the L1 instruction cache - Write-back L3 Cache (shared among cluster of cores) - 4MiB,16-way set associative The A77 TLB consists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally, there is a unified L2 TLB (STLB). The physical address is 40 bits. ITLB/DTLB (separate structures) - page size 16KiB - 48-entry fully associative STLB - 1280-entry 5-way set associative