Question 2. Pipelining Hazards (18 points) Consider the MIPS assembly code given below. We want to run this code on a 5-stage pipelined processor, with some modifications. The processor is a typical 5-stage pipeline (F-D-X-M-W), with the following exception . The multiplier block used to execute the mul instruction is pipelined into four stages: This means that a multiply instruction runs through the pipeline as follows: F-D-X0- X1-X2-X3-M-W and up to four multiply instructions maybe in-flight at a time. All other instruction types are blocked from the execute stage while any of the multiply stages are being used xor r0, r0, rO0 addiu r1, r0, 10 j L1 loop: lw r3, 0(r2) mul r4, r3, r:3 mul r3, r3, r1 addiu r0, r0, 1 sw r3, 0(r2) addiu r2, r2, 4 2 4 7 8 10 L1: bne r0, rl, -'7 Question 2. Pipelining Hazards (18 points) Consider the MIPS assembly code given below. We want to run this code on a 5-stage pipelined processor, with some modifications. The processor is a typical 5-stage pipeline (F-D-X-M-W), with the following exception . The multiplier block used to execute the mul instruction is pipelined into four stages: This means that a multiply instruction runs through the pipeline as follows: F-D-X0- X1-X2-X3-M-W and up to four multiply instructions maybe in-flight at a time. All other instruction types are blocked from the execute stage while any of the multiply stages are being used xor r0, r0, rO0 addiu r1, r0, 10 j L1 loop: lw r3, 0(r2) mul r4, r3, r:3 mul r3, r3, r1 addiu r0, r0, 1 sw r3, 0(r2) addiu r2, r2, 4 2 4 7 8 10 L1: bne r0, rl, -'7