See image first.

Before running the code, assume that the FC registers of interest contain the following values:

$$2$: $0$x$1$

$$3$: $0$xfffffff

$$4$: $0$x$0$

$$5$: $0$x$0$f$7$a

$$6$: $0$x$288$

$$7$: $0$x$1$

$$8$: $0$x$1003$ab$00$

$$9$: $010088b00$

$$10$: $0$x$1008$cb$00$

$$16$:$03$

$$17$:$0$x$0$

and the memory locations referenced by the code contain:

mem$[0x1003ab00]$: $0x1$

mem$[0x1003ab04]$: $0x0$

mem$[0x1003ab08]$: $0x7$

mem$[0x1003ab0c]$: $0x2$

mem$[0x1003ab10]$: $0x11$

mem$[0x1003ab14]$: $0x3$

mem$[0x1003ab18]$: $0x1$

mem$[0x1003ab1c]$: $0xa$

mem$[0x1003ab20]$: $0x2b$

mem$[0x10088b00]$: Oxffffffc

mem$[0x10088b04]$: $0x2a$

mem$[0x10088b08]$: $0x5$

mem$[0x10088b0c]$: $0x10088b24$

mem$[0x10088b24]$: $0x0$

mem$[0x10088b28]$: Oxe

mem$[0x10088b2c]$: Oxffffffff

mem$[0x10088b30]$: $0x10089b00$

mem$[0x10089b00]$: $0x2$

mem$[0x10089b04]$: $0x1d$

mem$[0x10089b08]$: $0x1$

mem$[0x10089b0c]$: $0x0$

mem$[0x1008cb00]$: $0x0$

Also, the DPU is empty and the control signals, as well as all history bits of the branch predictor subunit,

are set to zero. Assume that the addresses of the branch instructions do not conflict in accessing the

history memory and destination addresses. Show how the code is executed in the above NET, as

follows:

A$.$ Give the single timing diagram resulting from the run, based on the register and memory values listed

above.

B$.$ Provide all values generated within the DPU, either as data or control signals, separately for each

machine cycle, from the recall phase of the first instruction, to the result storage phase of the last

instruction. For this purpose, use the shown datapath, duplicating it as many times as needed, creating

in each empty DPU a snapshot of a machine cycle, placing on each the requested signal and data values.

Hint: In this exercise the flow of register and memory values results in three iterations.Consider MIPS DPU of partially overlapping instructions, with pipelining and branch prediction.