Shown in the following figure are two cascaded logic gates. Both gates are built with WN...

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Shown in the following figure are two cascaded logic gates. Both gates are built with WN = 125 nm and WP = 375 nm. Load capacitances are specified as CL1 = 3 ff for the first gate, and CL2= 5 ff for the second gate. Initially, both gates are in a static state with X1 = 0, X2 = 0 and X3 = 0. Now suppose that X1 and X3 simultaneously become logic-1. How much delay will it take for the voltage of Y to cross VDD/2 ? DD X₂ X₂ X₂- :С₁₁ DD DD VODO :CL2 0 Shown in the following figure are two cascaded logic gates. Both gates are built with WN = 125 nm and WP = 375 nm. Load capacitances are specified as CL1 = 3 ff for the first gate, and CL2= 5 ff for the second gate. Initially, both gates are in a static state with X1 = 0, X2 = 0 and X3 = 0. Now suppose that X1 and X3 simultaneously become logic-1. How much delay will it take for the voltage of Y to cross VDD/2 ? DD X₂ X₂ X₂- :С₁₁ DD DD VODO :CL2 0

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