sing the following Shift register with load$-$reducing NOT gates and any number of AND and

OR gates, design the following circuits; do not forget the CLOCK. $(2\mathrm{.}5$ Points$)$

$($a$)$ A Moore$-$model circuit that outputs $1$ if the last four input have been twice repeated alternating

$0$s and $1$s$,$ e$.$g$.,0011,1001,...,0110.(+1\mathrm{.}0)$

$($b$)$ A Mealy$-$model circuit which outputs $1$ if the last four input have been twice repeated alternating

$0$s and $1$s AND the current input correctly matches the pattern, e$.$g$.,$ x$001$