Single

-

cycle CPU implementation

We will implement a hypothetical instruction sw+ in the single

-

cycle pipeline. sw+ is

a store word, with post increment that is found in some real architectures. It is

encoded as an I

-

type instruction an

d performs the following operations:

Part (a) The single

-

cycle datapath from the lecture is shown below. Show what

changes are needed to support sw+ instruction. You should only add wires and muxes

to the datapath; do no modify the main functional un

its themselves (the memory,

register file and ALU). (20 points)

Note: Please make sure that the modification will no lengthen the clock cycle.

Assume that ALU, Memory, and Register file all take 2ns, and everything else is

instantaneous.

Part (b) On the diagram, write (next to the signals name) values of all control signals

required for the sw+ instruction. (10 points)