Sketch a schematic for a fast 3:8 decoder. Suppose gate delays are given in Table 2.8. Design your decoder using the gates in Table. 2.8 to have the shortest possible critical path. Indicate what the critical path is. What are the propagation delay and contamination delay?

Sketch a schematic for a fast 3:8 decoder. Suppose gate delays are given in Table 2.8. Design your decoder using the gates in Table. 2.8 to have the shortest possible critical path. Indicate what the critical path is. What are the propagation delay and contamination delay? Table 28 Gate delays for Exercises 2.43-2.47 Gate NOT 2-input NAND 3-input NAND 2-input NOR 3-input NOR 2-input AND 3-input AND 2-input OR 3-input OR 2-input XOR Ind (ps) 15 20 30 30 45 30 ted (ps) 10 15 25 25 35 25 30 30 45 40 60