Solve it for me using VHDL CODE please.

Q$1.$ Design by writing a VHDL code a shift register based on the following entity and simulation results: $[$

entity SR$1$ is

port$($clk$,$ rst$,$ sin: in bit;

s: in bit$\_$vector$(1$ downto $0)$;

d: in bit$\_$vector$(3$ downto $0)$;

q: out bit$\_$vector$(3$ downto $0))$;

end SR$1$;

Synthesis your design using Quartus Prime Lite Edition, and then simulate it using ModelSim Altera for all different combinations of the input variables.