Suppose a processor has two-level caches, L1 and L2, such that if a memory reference is an L1 miss, then L2 is checked. If L2 is still a miss, then the main memory is accessed. Let Ch1 = 4 CPU cycles and Ch2 = 40 CPU cycles be the time to access a word at L1 and L2 caches (assuming cache hits) respective. Among all memory references issued by a program, let m1= 20% and m2 = 10% be the miss ratios at the L1 and L2 caches, respectively, where the miss ratio at a cache is defined as the number of cache misses divided by the number of visits to that cache. Let the time to access a word at the main memory be 250 CPU cycles. What is the average time (in the unit of CPU cycles) to access a word in this program?