Suppose the DLX architecture is modified such that each instruction's excursions takes 8 clock cycles, where the ALU is slow and the execute phase needs more 3 clock cycles (E1, E2, and E3) and data memory takes 2 cycles (M1 and M2), if the ALU is not internally pipelined (i.e only one instruction can use the ALU), memory is not always pipelined (i.e only one instruction can access memory): IF ID Cycle 1 pipeline IF Busy flag E1 E2 2 ID 3 I E1 E3 4 E2 M1 M2 5 E3 6 M1 WB 7 M2 8 WB 1- Repeat problem 5 with the above 8 stages pipeline. 2- Assume that if the ALU is internally pipelined (there could be more than one instruction at a time in the ALU. Repeat problem 6 with the above 8 stages pipeline.