5. Suppose we have a 32-bit MIPS processor, which includes a 2-way set associative data cache with capacity 16384 bytes, 16 bytes block, and a least recently used (LRU) replace- ment policy. Assume that the cache is empty (all valid bits are 0) before the following code is executed 1w 1w lw lw lw lw t1, 0x1040 ($0) $t2, 0x2044 ($0) $t3, 0x3048 ($0) $t 4, 0x1044 ($0) $t5, 0x504c ($0) $t 6, 0x3040 ($0) 4 For each of the six assembly instructions above, state i) the set field value for the accessed address, i) the tag field value, and ii) if the instruction results in a cache hit or a cache miss