Task $1$: Pipelined Architecture$$

Assume you are programming in assembly on a $16-$bit architecture which employs a five$-$stage pipeline for instruction execution.$$

The five stages are:$$

$(1)$ fetch next instruction$$

$(2)$ decode instruction and fetch operands$$

$(3)$ perform ALU operation$$

$(4)$ read or write to memory$$

$(5)$ store result in register$$

Your architecture has $8$ general purpose registers split into two banks with r$0-$ r$3$ on bank $1$ and r$4-$ r$7$ on bank $2.$ The following instructions are implemented:$$