Task 2 [15 points]. An Arithmetic and Logical Unit (ALU) is an important hardware in processor's datapath. It is used to perform arithmetic and logical operations, such as add, subtract, logical AND, and logic OR. In this task, you will create a 32-bit ALU SystemVerilog module, using the given alu.sv with the following module declaration: module alu (input logic[31:0] a, b, input logic [1:] ALUControl, output logic[31:0] Result, output logic[3:0] ALUFlags); In the module, a and b are operands to the ALU. ALUControl determines the operation to be performed. Assume 00, 01, 10, and 11 for add, subtract, logical AND, and logical OR operations, respectively. The four bits of ALUFlags should be set to 1 if the given condition in the below table is met. SystemVerilog Testbench: Before writing the testbench, fill the missing cells in ALUControl, B, Result, and ALUFlags columns in Table 1. Now, write a testbench that takes ALU inputs from columns ALUControl, A, and B; and generates Result and ALUFlags. The produced outputs should be similar to Result and ALUFlags. Remember that each hexadecimal digit in the table represents 4 bits. Be careful when pulling signals from the file that are not multiples of four bits