$//$ Testbench

module test;

reg clk$\_$write;

reg $[4$:$0]$ address$\_$write;

reg $[7$:$0]$ data$\_$write;

reg write$\_$enable;

reg clk$\_$read;

reg $[4$:$0]$ address$\_$read;

wire $[7$:$0]$ data$\_$read;

$//$ Instantiate design under test

$//$ D$\_$WIDTH $=8$

$//$ A$\_$WIDTH $=5$

$//$ A$\_$MAX $=2^$A$\_$WIDTH $=32$

ram #$(8,5,32)$ RAM $($

$.$clk$\_$write$($clk$\_$write$),$

$.$address$\_$write$($address$\_$write$),$

$.$data$\_$write$($data$\_$write$),$

$.$write$\_$enable$($write$\_$enable$),$

$.$clk$\_$read$($clk$\_$read$),$

$.$address$\_$read$($address$\_$read$),$

$.$data$\_$read$($data$\_$read$)$

$)$;

initial begin

$//$ Dump waves

$dumpfile$("$dump$.$vcd$")$;

$dumpvars$(1,$ test$)$;

clk$\_$write $=0$;

clk$\_$read $=0$;

write$\_$enable $=0$;

address$\_$read $=5\text{'}$b$1\_1011$; $//$ Fixed binary format

address$\_$write $=5\text{'}$b$1\_1010$; $//$ Fixed binary format

$//$ Read initial data

$display$("$Read initial data."$)$;

toggle$\_$clk$\_$read;

$display$("$data$[\%0$h$]$: $\%0$h$",$ address$\_$read, data$\_$read$)$;

$//$ Write new data

$display$("$Write new data."$)$;

write$\_$enable $=1$;

data$\_$write $=8\text{'}$hF$0$;

toggle$\_$clk$\_$write;

write$\_$enable $=0$;

$//$ Read new data

$display$("$Read new data."$)$;

toggle$\_$clk$\_$read;

$display$("$data$[\%0$h$]$: $\%0$h$",$ address$\_$read, data$\_$read$)$;

end

task toggle$\_$clk$\_$write;

begin

#$10$ clk$\_$write $=$ ~clk$\_$write;

#$10$ clk$\_$write $=$ ~clk$\_$write;

end

endtask

task toggle$\_$clk$\_$read;

begin

#$10$ clk$\_$read $=$ ~clk$\_$read;

#$10$ clk$\_$read $=$ ~clk$\_$read;

end

endtask

endmodule $/*$

$*$ Random Access Memory $($RAM$)$ with

$*1$ read port and $1$ write port

$*/$

module ram $($clk$\_$write, address$\_$write,data$\_$write, write$\_$enable,

clk$\_$read, address$\_$read, data$\_$read$)$;

parameter D$\_$WIDTH $=32$;

parameter A$\_$WIDTH $=10$;

parameter A$\_$MAX $=10$; $//2^$A$\_$WIDTH

$//$ Write port

input clk$\_$write;

input $[$A$\_$WIDTH$-9$:$0]$ address$\_$write;

input $[$D$\_$WIDTH$-31$:$0]$ data$\_$write;

input write$\_$enable;

$//$ Read port

input clk$\_$read;

input $[$A$\_$WIDTH$-9$:$0]$ address$\_$read;

output $[$D$\_$WIDTH$-31$:$0]$ data$\_$read;

reg $[$D$\_$WIDTH$-31$:$0]$ data$\_$read;

$//$ Memory as an array of register variables

reg $[$D$\_$WIDTH$-31$:$0]$ memory $[$A$\_$MAX$-9$:$0]$;

$//$ Write data to memory

always @$($posedge clk$\_$write$)$ begin

if $($write$\_$enable$)$ begin

memory$[$address$\_$write$]<=$ data$\_$write;

end

end

$//$ Read data from memory

always @$($posedge clk$\_$read$)$ begin

data$\_$read $<=$ memory$[$address$\_$read$]$;

end

endmodule can you fix this code for me