testbench.sv

module testCPU;

reg clk$,$ reset;

wire $[7$:$0]$ DMem;

int errors $=0$;

reg $[7$:$0]$ DMem$\_$expected$[4$:$0]$;

integer i$,$ j;

top$\_$CPU CPU$0($

$.$D$\_$rd$\_$data$($DMem$),$

$.$clk$($clk$),$

$.$reset$($reset$)$

$)$;

always #$5$ clk $=$ ~clk;

initial begin

$dumpfile$("$dump$.$vcd$")$;

$dumpvars$(2)$;

$readmemb$("$Dmem$\_$expected.tv$",$ DMem$\_$expected, $0,4)$;

i $=0$;

j $=0$;

clk $=1\text{'}$b$0$;

reset $=1\text{'}$b$1$;

$display$("$Reset$")$;

#$26$ reset $=0$;

end

always @$($negedge clk$)$ begin

if $(!$reset$)$ begin

if $(($i $>7)$ && $($i $<=12))$ begin

if $($DMem $!==$ DMem$\_$expected$[$j$])$ begin

$display$("$# ERROR: i$=\%0$d$,$ j$=\%0$d$,$ DMem$=\%0$d$,$ DMem$\_$expected$=\%0$d$",$ i$,$ j$,$ DMem, DMem$\_$expected$[$j$])$;

errors $=$ errors $+1$;

end else begin

$display$("$# CORRECT: i$=\%0$d$,$ j$=\%0$d$,$ DMem$=\%0$d$,$ DMem$\_$expected$=\%0$d$",$ i$,$ j$,$ DMem, DMem$\_$expected$[$j$])$;

end

j $=$ j $+1$;

end

if $($i $>12)$ begin

$display$("$# of Errors $=\%$d$",$ errors$)$;

$finish;

end

i $=$ i $+1$;

end

end

endmodule

Dmem$\_$expected.tv

$0000\_0001$

$0000\_0001$

$0000\_0010$

$0000\_0011$

$0000\_0101$

design.sv

$`$include "controller.sv$"$

$`$include "registerfile.sv$"$

$`$include "ALU.sv$"$

$`$include "memories.sv$"$

$`$include "parameterized$\_$mux.sv$"$

module top$\_$CPU$($

input clk$,$

input reset,

output $[7$:$0]$ D$\_$rd$\_$data

$)$;

wire RF$\_$W$\_$we$,$ DMEM$\_$we;

wire $[1$:$0]$ ALUcontrol, Mux$\_$M$0,$ Mux$\_$M$1$;

wire $[11$:$0]$ instruction;

wire $[7$:$0]$ alu$\_$result, A$,$ B$,$ DMem;

wire $[5$:$0]$ address;

$//$ Instantiate the controller

controller ctrl$($

$.$opcode$($instruction$[11$:$9]),//$ Opcode bits

$.$RF$\_$W$\_$we$($RF$\_$W$\_$we$),$

$.$DMEM$\_$we$($DMEM$\_$we$),$

$.$ALUcontrol$($ALUcontrol$),$

$.$Mux$\_$M$0($Mux$\_$M$0),$

$.$Mux$\_$M$1($Mux$\_$M$1)$

$)$;

$//$ Instantiate the ALU

ALU alu$($

$.$Result$($alu$\_$result$),$

$.$ALUcontrol$($ALUcontrol$),$

$.$A$($A$),//$ Operand A

$.$B$($B$)//$ Operand B

$)$;

$//$ Instantiate the register file

register$\_$file rf$($

$.$clk$($clk$),$

$.$reset$($reset$),$

$.$R$1\_$addr$($instruction$[8$:$6]),//$ Source register $1$

$.$R$2\_$addr$($instruction$[5$:$3]),//$ Source register $2$

$.$W$\_$addr$($instruction$[2$:$0]),//$ Destination register

$.$W$\_$data$($alu$\_$result$),//$ Data to write

$.$W$\_$we$($RF$\_$W$\_$we$),//$ Write enable

$.$R$1\_$data$($A$),//$ Output to ALU A

$.$R$2\_$data$($B$)//$ Output to ALU B

$)$;

$//$ Instantiate data memory

dmem memory$($

$.$clk$($clk$),$

$.$we$($DMEM$\_$we$),$

$.$addr$($address$),$

$.$wr$\_$data$($B$),//$ Data to write comes from register file $($B$)$

$.$rd$\_$data$($DMem$)//$ Data read from memory

$)$;

$//$ Instruction memory

imem instruction$\_$memory$($

$.$addr$($address$[3$:$0]),//$ Instruction address

$.$rd$\_$data$($instruction$)//$ Instruction output

$)$;

$//$ Multiplexer to select data from ALU or memory

Mux$2$x$1$ #$(.$N$(8))$ mux$1($

$.$in$0($alu$\_$result$),//$ ALU result

$.$in$1($DMem$),//$ Data from memory

$.$sel$($Mux$\_$M$1[0]),//$ Select signal

$.$out$($D$\_$rd$\_$data$)//$ Output

$)$;

$//$ Generate address

assign address $=$ instruction$[5$:$0]$; $//$ Use instruction address bits

endmodule

register.sv

module register$\_$file $($

input wire clk$,$

input wire reset,

input wire $[2$:$0]$ R$1\_$addr,

output reg $[7$:$0]$ R$1\_$data,

input wire $[2$:$0]$ R$2\_$addr,

output reg $[7$:$0]$ R$2\_$data,

input wire $[2$:$0]$ W$\_$addr,

input wire $[7$:$0]$ W$\_$data,

input wire W$\_$we

$)$;

reg $[7$:$0]$ rf $[7$:$0]$; $//8$ registers, each $8$ bits wide

$//$ Read ports

always @$(*)$ begin

R$1\_$data $=$ rf$[$R$1\_$addr$]$;

R$2\_$data $=$ rf$[$R$2\_$addr$]$;

$display$("$# DEBUG: Reading R$1\_$data$=\%0$d$,$ R$2\_$data$=\%0$d$",$ R$1\_$data, R$2\_$data$)$;

end

$//$ Write port

always @$($posedge clk or posedge reset$)$ begin

if $($reset$)$ begin

integer i;

for $($i $=0$; i $<8$; i $=$ i $+1)$ begin

rf$[$i$]<=8\text{'}$b$0$;

end

$display$("$# DEBUG: Resetting register file."$)$;

end else if $($W$\_$we$)$ begin

rf$[$W$\_$addr$]<=$ W$\_$data;

$display$("$# DEBUG: Writing $\%0$d to rf$[\%0$d$]",$ W$\_$data, W$\_$addr$)$;

end

end

endmodule

parameterized$\_$mux.sv

module Mux$2$x$1$ #$($parameter N $=8)($

input $[$N$-1$:$0]$ in$1,$

input $[$N$-1$:$0]$ in$0,$

input sel,

output $[$N$-1$:$0]$ out

$)$;

assign out $=$ sel $?$ in$1$ : in$0$; $//$ Select between in$1$ and in$0$

endmodule

Please help me to all of this code have the correct ouput like this output:Reset

# CORRECT: i$=8,$ j$=0,$ DMem$=1,$ DMem$\_$expected$=1$

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