Text:

Suppose that we have a processor with two levels of cache hierarchy. The L1 cache is direct mapped and contains two lines. The L2 cache is fully associative and has four lines. The L2 cache is inclusive of the L1 cache, and inclusion is enforced by a multi-level cache inclusion protocol. Both the L1 and L2 caches use LRU replacement policy. Assume that blocks A, B, C, D map to the first line in the L1 cache, while blocks U, V, W, X map to the second line in the L1 cache. Each block has either a Valid (V) or Invalid (I) state.

Show the outcome of each read access (H for Hit, M for Miss, MR-X for Miss and Replace block X) and show the final cache content (Write block name A,B,C,D etc. under 'Which Block?' column, and 'Valid' or 'Invalid' under 'What State?' column)

Since the L2 cache is fully associative, fill in its final cache contents in alphabetical order.

(Also show tables where 1.L2 uses a non-inclusive policy and 2.L2 uses an exclusive policy. Both use the same table format as the image shown below)

Image:

Invalid (1) state. Since the L2 cache is fully associative, fill in its final cache contents in alphabetical order. Final Cache Content