The countdown module will either count down from 8, or count down from 4. When the FSM is IDLE, pressing A causes the count down from 8, pressing B causes the count down from 4. In state T1, pressing B resets the count down to 4. Pressing A means setting A to 1. Pressing B means setting B to 1. The FSM is:

The states are defined as:

typedef enum logic[3:0] { T8, T7, T6, T5, T4, T3, T2, T1, IDLE } countdown_st_t; 

Complete the countdown module using behavioural Verilog

module countdown( output countdown_st_t state, input logic A, B, input logic clk, reset );

endmodule

:

B -A and B -B T8 T7 T6 TS T4 T3 T2 T1 -A and B A