The data flow graph (DFG) given in Figure Q1 shows the operations and data dependencies of...

   

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The data flow graph (DFG) given in Figure Q1 shows the operations and data dependencies of a digital system to be designed. a, b, c, d and e are all 8-bit data inputs that are registered in the initial state and f is the output. (b) (c) (d) If the design is constrained to three arithmetic units, where each arithmetic unit contains a multiplier and an adder. Construct the schedule of this DFG applying "as soon as possible" (ASAP) scheduling. (8 marks) Derive the corresponding RTL code for your design. Obtain the fbd of the datapath unit of this digital system. Obtain the fbd of the control unit showing all the control signals. X (8 marks) (e) It is given that the propagation delay of the components are as follows: the adder is 30 ns, multiplier is 130 ns and register is 10 ns. Calculate the maximum operating frequency of your design. (5 marks) + (6 marks) Figure Q1 (8 marks) The data flow graph (DFG) given in Figure Q1 shows the operations and data dependencies of a digital system to be designed. a, b, c, d and e are all 8-bit data inputs that are registered in the initial state and f is the output. (b) (c) (d) If the design is constrained to three arithmetic units, where each arithmetic unit contains a multiplier and an adder. Construct the schedule of this DFG applying "as soon as possible" (ASAP) scheduling. (8 marks) Derive the corresponding RTL code for your design. Obtain the fbd of the datapath unit of this digital system. Obtain the fbd of the control unit showing all the control signals. X (8 marks) (e) It is given that the propagation delay of the components are as follows: the adder is 30 ns, multiplier is 130 ns and register is 10 ns. Calculate the maximum operating frequency of your design. (5 marks) + (6 marks) Figure Q1 (8 marks)