Question: The following code is executing on a five - stage processor. The two instructions cause exceptions ( stage where fault occurs are bolded ) :ld

The following code is executing on a five

-

stage processor. The two instructions cause exceptions

(

stage where fault occurs are bolded

)

:ld a

0, 0 (

)

FDXMWmemory permission violationbnea

2, 3,

FDXM Wmisaligned PC on branch targetIf the processor implements precise exceptions, which exception is handled first?Why? What happens to the other instruction and exception?

1

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