The following given Verilog modules are for the next two questions. /D flip-flap with asynchronaus reset module DFF (output reg 0. input D, Clk, RstH always @(posedge Clk, posedge Rst) module count4 output [3: 0. input Clk. input Rst) wire a, b, c, d assign a -0I11: assign b 012]: assign c-013 assign d = Q[01 endrodule The module count4 counts in a special way. 8. What is the next output Q[310[2]Q[1jQ[0] after 0000? A. O 0001 B. O 0011 C. O 1100 D. 0010 E. 00110 9. In the above question, What is the next output Q[3]Q[2]Qt1jQ[0] after 0110? (Be careful that the leftmost bit in the answer is Q[3] and the rightmost bit is Q[0].) A. 0010 B. 1001 C. O 1100 D. 00000 E. O 0110