Question: The following program is running on the 5-stage pipelined processor shown in class. Assume that all registers are initialized to 0. lw $r1, 8($r5) lw

The following program is running on the 5-stage pipelined processor shown

The following program is running on the 5-stage pipelined processor shown in class. Assume that all registers are initialized to 0. lw $r1, 8($r5) lw $r2, 16($r4) sub $r7, $r1, $r2 beq $r9, $r7, label add $r1, $r10, $r11 label: lw $r12, 4($r3) and $r4, $r12 $r7 (a) Draw arrows to show all data dependencies between instructions. lw $r1, 8($r5) lw $r2, 16($r4) sub $r7, $r1, $r2 beq $r9, $r7, label add $r1, $r10, $r11 sw $r6, 0($r1) label: lw $r12, 4($r3) and $r4, $r12, $r7

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