The following state table is implemented using a ROM and two D ip$-$ops $($falling edge triggered$)$:

Q$1$Q$2$ Q$1$

$1$Q$2$

$1$ Z

X $50$ X $51$ X $50$ X $51$

$00011001$

$01100011$

$10000110$

$($a$)$ Draw the block diagram.

$($b$)$ Write VHDL code that describes the system. Assume that the ROM has a delay of $10$ ns$,$ and each ip$-$op

has a propagation delay of $15$ ns$.$