The Intel 8088 microprocessor has a read bus timing similar to that of the figure shown below, but requires four(4) processor clock cycles. The valid data is on the bus for an amount of time that extends into the fourth processor clock cycle. Assume a processor clock rate of 8 MHz.

What is the maximum data transfer rate?

Repeat, but assume the need to insert one wait state per byte transferred.

Timing of Synchronous Bus Operations Clock Status lines Status signals Address lines Address enable Data Read lines Valid data in cycle Read Data Writelines Valid data out cycle Write