Question: The memory hierarchy contains a single cache with a miss rate of 2% that holds both instructions and data. The miss penalty to access main

The memory hierarchy contains a single cache with a miss rate of 2% that holds both instructions and data. The miss penalty to access main memory is 100 cycles. 15% of the instructions are jumps, 20% are stores, 20% are loads (30% have values used in the next instruction), 10% are branches (taken 20% of the time) and 35% are ALU instructions. Jumps and branches are determined in the ID stage. What is the base CPI? What is the effective CPI?

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