A machine has an instruction cache with a miss rate of $1\%$ and a data cache with a miss rate of $5\%$ and $35\%$ of the total instructions are loads and stores. Both caches have a hit time of one clock cycle. The data cache writes back $$ on average $25\%$ of the blocks in the cache are dirty. Address translation is handled by a TLB with a miss rate of $0\mathrm{.}5\%$ and a miss penalty of $92$ clock cycles. The main memory has a latency of $90$ clock cycles. Please note that all caches in Problem $1$ are virtual.

Assuming that your goal is to minimize the average memory access time, which of the options below would you choose? Must show work.

Option $1$:

Add a secondary instruction cache with an access time of $10$ clock cycles that reduces the global miss rate of fetches to $0\mathrm{.}6\%$;

Option $2$:

Add a unified second$-$level cache with an access time of $8$ clock cycles and a local miss rate of $50\%.$