The objective is to add the microprocessor that was designed in lab 5 with Data Path, ALU and CPU Control, Memory Reference (LW, SW) and Flow Control Instructions.

Based on the microprocessor that you had designed in Lab 5, we will add the following

instructions:

LW
SW
BEQ

The central controller decodes the currently fetched instruction and generates control fields based on the type of instructions, see figure. Based on these control fields, appropriate register file is read and fed to the ALU. The ALU also needs an ALU Control module which will generate necessary ALU function fields based on controller’s field and instruction’s function code. After ALU completes its operation, we have to write back ALU result to destination register or memory based on control fields.

When branch is required, update PC with an offset. Else, proceed with normal PC increment, which is 4. For BEQ, use arithmetic subtracts of ALU and generate “Zero” control field if the result of subtraction is a zero.

Design and simulate the CPU module with central Control unit, ALU control, arithmetic and logic instructions, memory reference and flow control instructions. Test the following instructions and show the waveform result.

Instruction0: AND: R0 = R1&R2;
Instruction1: OR: R0 = R1|R2;
Instruction2: ADD: R0 = R3+R4;
Instruction3: SUB: R0 = R3-R4;

Instruction4: SW: R4, 5(R1), data_memory[5 + R1] = R4
Instruction5: LW: R0, 5(R1); R0 = data_memory[5 + R1]
Instruction6: BEQ: R3, R5, 2; If R3 = R5, PC = PC + 2*4; else PC = PC+4

Instruction9: OR: R0 = R1|R2;
Instruction10: AND: R0 = R1&R2;
Instruction11: OR: R0 = R1|R2;
Instruction12: ADD: R0 = R3+R4;
Instruction13: SUB: R0 = R3-R4;

R1 = 32'h00000000;
R2 = 32'hFFFFFFFF;
R3 = 32'h00000005;
R4 = 32'h00000004;
R5 = 32'h00000005;

Your outputs should at least include ALU_result, data_memory[5], and Register_File[0] (R0)