This exercise explores energy

efficiency and its relationship with performance. Problems in this exercise assume the following energy consumption for activity in Instruction memory, Registers, and Data memory. You can assume that the other components of the datapath consume a negligible amount of energy. (Register Read and Register Write refer to the register le only.)

I-Mem	1 Register Read	Register Write	D-Mem Read	D-Mem Write
140pJ	70pJ	60pJ	140pJ	120pJ

Assume that components in the datapath have the following latencies. You can assume that the other components of the datapath have negligible latencies.

I-Mem	Control	Register Read or Write	ALU	D-Mem Read or Write
200 ps	150 ps	90 ps	90 ps	250 ps

4.32.1 [5] <4.3, 4.6, 4.14> How much energy is spent to execute an ADD instruction in a single-cycle design and in the ve-stage pipelined design?

4.32.2 [10] <4.6, 4.14> What is the worst-case ARMv8 instruction in terms of energy consumption? What is the energy spent to execute it?

4.32.3 [10] <4.6, 4.14> If energy reduction is paramount, how would you change the pipelined design? What is the percentage reduction in the energy spent by an LDUR instruction a er this change?

4.32.4 [10] <4.6, 4.14> What other instructions can potentially bene t from the change discussed in Exercise 4.32.2?

4.32.5 [10] <4.6, 4.14> How do your changes from Exercise 4.32.3 a ect the performance of a pipelined CPU?

4.32.6 [10]<4.6,4.14>WecaneliminatetheMemReadcontrolsignalandhave the data memory be read in every cycle, i.e., we can permanently have MemRead=1. Explain why the processor still functions correctly a er this change. If 25% of instructions are loads, what is the e ect of this change on clock frequency and energy consumption?