This problem explores energy efficiency and its relationship with performance. The parts of this problem assume the following energy consumption for activity in Instruction memory, Registers, and Data memory. You can assume that the other components of the datapath consume a negligible amount of energy. "Register Read" and "Register Write" refer to the register file only.$)$

$\backslash$table$[[1-$Mem,$1$ Register Read,Register Write,D$-$Mem Read,D$-$Mem Write$],[140$p$,70$pl$,60$p$],140$p$),120$py$]]$

Assume that components in the datapath have the following latencies. You can assume that the other components of the datapath have negligible latencies.

$\backslash$table$[[$I$-$Mem Control$],[$Register Read or Write,ALU,D$-$Mem Read or Write,,$],[200$ po$,150$ po$,90$ ps$,90$ ps$,250$ ps$]]$

$4\mathrm{.}1$ How much energy is spent to execute an addi instruction in a single$-$cycle design and in the five$-$stage pipelined design

$4\mathrm{.}2$ How much energy is spent to execute a lw instruction in a single$-$cycle design

$4\mathrm{.}3$ How much energy is spent to execute a beq instruction in a single$-$cycle design