This exercise explores energy efficiency and its relationship with performance Problems in this exercise assume the following energy consumption for activity in Instruction memory, Registers, and Data memory. You can assume that the other components of the datapath spend a negligible amount of energy D-Mem Read D-Mem Write I-Mem 1 Register Register Write Read 140pJ 70pJ 60pJ 140pJ 120pJ Assume that components in the datapath have the following latencies. You can assume that the other components of the datapath have negligible latencies. I-Mem Control |Register Read or ALUD-Mem Read or Write Write 200ps 150ps 90ps 250ps a. How much energy is spent to execute an ADD instruction in a single-cycle design and in the 5-stage pipelined design? b. What is the worst-case MIPS instruction in terms of energy consumption, and what is the energy spent to execute it? c. If energy reduction is paramount, how would you change the pipelined design? What is the percentage reduction in the energy spent by an LW instruction after this change? d. What is the performance impact of your changes from c