This is the code for a 4 bit adder in verilog. Can you please write code to turn this into a 4 bit adder / subtractor without using any XOR gates. Also explain to me why in assign (c_out, sum) = a + b + c_in we know that c_out will have value of the overflow?

1 2 3 module fulladd (input [3:0] a, input [3:0] b, input c_in, output c_out, output [3:0] sum); 4 5 6 6 7 assign {c_out, sum} = a + b + c_in; endmodule 8