Question: this verilog code is about stopwatch module stopwatch ( input wire clk , input wire reset, input wire start, input wire stop, input wire css

this verilog code is about stopwatch
module stopwatch (
input wire clk,
input wire reset,
input wire start,
input wire stop,
input wire css,
output reg [3:0] B1,
output reg [3:0] B0,
output reg [3:0] Bm1,
);
reg [3:0] sec_1, sec_0, min_1, min_0;
reg [3:0] best_sec_1, best_sec_0, best_min_1, best_min_0;
reg running;
reg [13:0] counter;
always @(posedge clk or posedge reset) begin
if (reset) begin
sec_1=4'b0000;
sec_0=4'b0000;
min_1=4'b0000;
min_0=4'b0000;
best_sec_1=4'b1001;
best_sec_0=4'b1001;
best_min_1=4'b1001;
best_min_0=4'b1001;
counter =14'b0;
running =0;
end else if (start) begin
sec_1=4'b0000;
sec_0=4'b0000;
min_1=4'b0000;
min_0=4'b0000;
counter =14'b0;
running =1;
end else if (stop) begin
running =0;
end else if (css && running) begin
if ({min_1, min_0, sec_1, sec_0}{best_min_1, best_min_0, best_sec_1, best_sec_0}) begin
best_sec_1= sec_1;
best_sec_0= sec_0;
best_min_1= min_1;
best_min_0= min_0;
end
end else if (running) begin
counter = counter +1;
if (counter ==14'b10011100010000) begin //10000 clock cycles for 0.01s
counter =0;
if (sec_0==4'b1001) begin
sec_0=4'b0000;
if (sec_1==4'b1001) begin
sec_1=4'b0000;
if (min_0==4'b1001) begin
min_0=4'b0000;
if (min_1==4'b1001) begin
min_1=4'b0000;
end else begin
min_1= min_1+1;
end
end else begin
min_0= min_0+1;
end
end else begin
sec_1= sec_1+1;
end
end else begin
sec_0= sec_0+1;
end
end
end
end
always @(*) begin
B1= min_1;
B0= min_0;
Bm1= sec_1;
Bm2= sec_0;
end
endmodule
and this is testbench
`timescale 1ns /1ps
module tb_stopwatch;
reg clk;
reg reset;
reg start;
reg stop;
reg css;
wire [3:0] B1;
wire [3:0] B0;
wire [3:0] Bm1;
wire [3:0] Bm2;
stopwatch uut (
.clk(clk),
.reset(reset),
.start(start),
.stop(stop),
.css(css),
.B1(B1),
.B0(B0),
.Bm1(Bm1),
.Bm2(Bm2)
);
always begin
#50 clk = ~clk;
end
initial begin
clk =0;
reset =1;
start =0;
stop =0;
css =0;
#100 reset =0;
#100 reset =1;
#100 start =1;
#100 start =0;
#100000;
#100 stop =1;
#100 stop =0;
#1000 css =1;
#1000 css =0;
#100 reset =1;
#100 reset =0;
#200 $finish;
end
initial begin
$monitor("Time: %d%d.%d%d | Best Time: %d%d.%d%d",
B1, B0, Bm1, Bm2,
uut.best_min_1, uut.best_min_0,
uut.best_sec_1, uut.best_sec_0);
end
endmodule
then i simulate, but waveform is like that picture
but i want waveform that when i start, bm2 increases 0>1>2>3.
and i want to see stop and css's waves.
why stop and css are only 0 in that picture...
please modify codes please...
this verilog code is about stopwatch module

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