Question: module Simplecomp ( input wire clk , input wire reset, input wire [ 1 5 : 0 ] data _ in , output wire [

module Simplecomp(
input wire clk,
input wire reset,
input wire [15:0] data_in,
output wire [15:0] data_out,
output wire [7:0] addr_out
);
// Memory Address Register
reg [7:0] MAR;
// Memory Buffer Register
reg [15:0] MBR;
// Program Counter
reg [7:0] PC;
// Instruction Register
reg [15:0] IR;
// General Purpose Registers
reg [15:0] R[7:0];
always @(posedge clk or posedge reset) begin
if (reset) begin
PC <=8'b0;
MAR <=8'b0;
MBR <=16'b0;
IR <=16'b0;
for (integer i =0; i <8; i = i +1) begin
R[i]<=16'b0;
end
end else begin
// Fetch instruction
MAR <= PC;
IR <= MBR;
PC <= PC +1;
// Decode and execute instruction
case (IR[15:13])
3'b000: // LOAD
if (IR[11:10]==2'b00) begin // Direct memory address
MAR <= IR[7:0];
R[IR[12:10]]<= MBR;
end else if (IR[11:10]==2'b01) begin // Register
R[IR[12:10]]<= R[IR[7:0]];
end else if (IR[11:10]==2'b10) begin // Register Indirect
MAR <= R[IR[7:0]];
R[IR[12:10]]<= MBR;
end else if (IR[11:10]==2'b11) begin // Constant
R[IR[12:10]]<= IR[7:0];
end
3'b001: // STORE
MAR <= IR[7:0];
MBR <= R[IR[12:10]];
3'b010: // ADD
R[IR[12:10]]<= R[IR[12:10]]+ R[IR[7:0]];
3'b011: // SUB
R[IR[12:10]]<= R[IR[12:10]]- R[IR[7:0]];
3'b100: // MUL
R[IR[12:10]]<= R[IR[12:10]]* R[IR[7:0]];
3'b101: // DIV
R[IR[12:10]]<= R[IR[12:10]]/ R[IR[7:0]];
endcase
end
end
assign data_out = MBR;
assign addr_out = MAR;
endmodule

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