Time left 0:59:07 Complete the behavioral VHDL code of an Arithmetic Logic Unit that has 4 inputs A, B, f and EN. A and B are 16 bits each, f is 3 bits and EN is 1 bit. The ALU has one output s that has a size of 16 bits. The below table shows the behavior of the Logic Unit. Note that any change on any input will affect the output. EN f S OX s will keep its value 1 000 S=A-B 1 001 S=A+B 1 010 S = B 1 011 S = A 1 100 s is cleared 1 101 s = A OB S 1 110 All the bits of s are set to 1 Most significant byte of s equals most significant Byte of A 1 111 Least significant byte of s equals least significant byte of B LIBRARY ieee ; Time left 0:58:55 LIBRARY ieee; USE USE ENTITY alu IS PORT (f: EN: AB: S: END alu; ARCHITECTURE Behavior OF alu IS BEGIN BEGIN If THEN CASE IS SD THEN If Time left 0:58:45 IS CASE S WHEN "010" => WHEN "011" => WHEN "100" => S S f S '0' S '1); WHEN "101" => WHEN others => A(15 DOWNTO 8) CASE, B(7 DOWNTO 0) IF; PROCESS, Behavior; S = A S