Question: timescale ins / lps module mainfunction (input a, b, c, output Y); assign y=(a&b) I (ac); endmodule timescale lns / Ips module testbench; reg a,b,c;

timescale ins / lps module mainfunction (input a, b, c, output

timescale ins / lps module mainfunction (input a, b, c, output Y); assign y=(a&b) I (ac); endmodule timescale lns / Ips module testbench; reg a,b,c; mainfunction dt (.a (a),.b(b),.c(c), y(Y)); initial begin a=0; b=0; c=0; #10 if (y!==1) $display("y=logic 0"); endmodule Which of the following is true for the two verilog codes above? 1. Behavioral design level is used. 11. Output(y) is equal to logic 1 and the text y=logic 0 appears in the simulation. III. The combinational circuit designed in the code includes 3 logic gates. IV. A net has to be added to the code for the output

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