Two important parameters control the performance of a processor: cycle time and cycles per instruction (CPI). There is an enduring trade-off between these two parameters in the design process of microprocessors. While some designers prefer to increase the processor frequency at the expense of large CPI, other designers follow a different school of thought in which reducing the CPI comes at the expense of lower processor frequency. Consider the following machines and compare their performance using the following instruction mix: 25% loads, 13% stores, 47% ALU instructions, and 15% branches/jumps. Assume the unmodified multi-cycle data path and finite state machine. - M1: The multicycle data path is designed with a 1GHz clock. - M2: A machine like M1 except that register updates are done in the same clock cycle as a memory read of ALU operation. Thus in the finite state machine, states 6 and 7 and states 3 and 4 are combined. This machine has an 3.2GHz clock, since the register update increases the length of the critical path. - M3: A machine like M2 except that effective address calculations are done in the same clock cycle as a memory access. Thus states 2, 3, and 4 can be combined, as can 2 and 5, as well as 6 and 7 . This machine has a 2.8GHz clock because of the long cycle created by combining address calculation and memory access. (a) Find out which of the machines are the fastest. (15 marks) (b) Are there instruction mixes that would make another machine faster, and if so, what are they? (10 marks)