Type a test bench for this vhdl code for a scoreboard.

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY scoreboard IS

PORT(clk1, clk2, reset : in STD_LOGIC;

segm1 : out STD_LOGIC_VECTOR( 6 DOWNTO 0);

segm2 : out STD_LOGIC_VECTOR( 6 DOWNTO 0));

END scoreboard;

ARCHITECTURE structure OF scoreboard IS

SIGNAL temp2: STD_LOGIC_VECTOR( 3 DOWNTO 0);

SIGNAL temp3: STD_LOGIC_VECTOR( 3 DOWNTO 0);

COMPONENT updowncnt

PORT ( clk1, clk2, reset : in STD_LOGIC;

q1 : out STD_LOGIC_VECTOR( 3 DOWNTO 0);

q2 : out STD_LOGIC_VECTOR( 3 DOWNTO 0));

END component;

COMPONENT display

PORT (A : in STD_LOGIC_VECTOR(3 DOWNTO 0);

B : in STD_LOGIC_VECTOR( 3 DOWNTO 0);

C : out STD_LOGIC_VECTOR(6 DOWNTO 0);

D : out STD_LOGIC_VECTOR(6 DOWNTO 0));

END COMPONENT;

BEGIN

u1: updowncnt PORT MAP ( clk1, clk2, reset, temp2, temp3);

d1: display PORT MAP ( temp2, temp3, segm1, segm2);

END structure;