can you please write the test bench for this VHDL

library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all;

entity ff is port( clk : in STD_LOGIC; reset : in STD_LOGIC; dout : out STD_LOGIC_VECTOR(3 downto 0) ); end ff;

architecture beh of ff is begin

counting : process (clk,reset) is variable m : std_logic_vector (3 downto 0) := "0000"; begin if (reset='1') then m := "0000"; elsif (rising_edge (clk)) then m := m + 1; end if; dout <= m; end process;

end beh;