Use the adder code below to make a subrator

library IEEE;

use IEEE.STD_LOGIC_1164.all;

use IEEE.STD_LOGIC_unsigned.all;

entity adder4b is

port(

a : in STD_LOGIC_VECTOR(3 downto 0);

b : in STD_LOGIC_VECTOR(3 downto 0);

s : out STD_LOGIC_VECTOR(3 downto 0);

cf : out STD_LOGIC;

ovf : out STD_LOGIC

);

end adder4b;

architecture adder4b of adder4b is

begin

process(a, b)

temp : STD_LOGIC_VECTOR(4 downto 0);

begin

temp := ('0' & a) + ('0' & b);

s<=temp(3 downto 0);

cf<= temp(4);

ovf<=temp(3) xor a(3) xor b(3) xor temp(4);

s<=a+b;

end process;

end adder4b;