Compile and simulate the behavioral description of the 4-bit adder in Figure 3-49. Assuming a ripple carry implementation, apply combinations that check out the rightmost full adder for all eight input combinations. Also apply combinations that check the carry chain connections between all full adders by demonstrating that a 0 and a 1 can be propagated from C₀ to C₄.

Figure 3-49

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--4-bit Adder: Behavioral Description library ieee; use use ieee.std_logic_1164.all; ieee.std_logic_unsigned.all; entity adder_4_b is. port (B, A: in std_logic_vector (3 downto 0); CO in std logic; S out std_logic_vector (3 downto 0); C4: out std_logic); end adder_4_b; architecture behavioral of adder_4_b is signal sum: std_logic_vector (4 downto 0); begin sum