Using Figure 3-49 as a guide and a when-else on S from Figure 3-29, write a high-level

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Using Figure 3-49 as a guide and a “when-else” on S from Figure 3-29, write a high-level behavior VHDL description for the adder–subtractor in Figure 3-46 (see Figure 3-45 for details). Compile and simulate your description.
Assuming a ripple carry implementation, apply combinations that check out one of the full adder–subtractor stages for all 16 possible input combinations. Also, apply combinations to check the carry chain connections in between the full adders by demonstrating that a 0 and a 1 can be propagated from C0 to C4. Check the overflow signals as well.

Figure 3-49

--4-bit Adder: Behavioral Description library ieee; use use ieee.std_logic_1164.all;

Figure 3-46

a  C-1 n-bit Adder/SubtractorFigure 3-45

J B3 A3 FA S3  B A FA S S B A FA S C  Ao FA So Co

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Related Book For  answer-question

Logic And Computer Design Fundamentals

ISBN: 9780133760637

5th Edition

Authors: M. Morris Mano, Charles Kime, Tom Martin

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