Using a table similar to that shown in Figure 3.10, show the steps of dividing unsigned 12-bit integer 87 by unsigned 6-bit integer 19 using the hardware described in Figure 3.8.

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Divisor Shift right 64 bits Quotient 64-bit ALU Shift left 32 bits Remainder Control test Write 64 bits FIGURE 3.8 First version of the division hardware. The Divisor register, ALU, and Remainder register are all 64 bits wide, with only the Quotient register being 32 bits. The 32-bit divisor starts in the left half of the Divisor register and is shifted right 1 bit each iteration. The remainder is initialized with the dividend. Control decides when to shift the Divisor and Quotient registers and when to write the new value into the Remainder register. Divisor Shift right 64 bits Quotient 64-bit ALU Shift left 32 bits Remainder Control test Write 64 bits FIGURE 3.8 First version of the division hardware. The Divisor register, ALU, and Remainder register are all 64 bits wide, with only the Quotient register being 32 bits. The 32-bit divisor starts in the left half of the Divisor register and is shifted right 1 bit each iteration. The remainder is initialized with the dividend. Control decides when to shift the Divisor and Quotient registers and when to write the new value into the Remainder register