Using Quartus 2 software:

Create one VHDL (alu32.vhd) that has exactly the same format as follows.

 library ieee; use IEEE.STD_LOGIC_1164.all; use IEEE.std_logic_misc.all; use IEEE.std_logic_arith.all; 

 entity alu32 is port( 

a, b : in STD_LOGIC_VECTOR(31 downto 0);

ALUControl : in STD_LOGIC_VECTOR(1 downto 0);

Result : buffer STD_LOGIC_VECTOR(31 downto 0);

ALUFlags : out STD_LOGIC_VECTOR(3 downto 0)

);

end alu32;

After running the compiler:

Error (12007): Top-level design entity "Lab2" is undefined.

Question: Please explain how to resolve the error and how to get this code to compile.