Using the operational timing:

Memory units: 300 ps

ALU and Adders: 100 ps

Register file (read or write): 200 ps

And incorporating the instruction mix:

Loads: 25%

Stores: 5%

ALU: 60%

Branches: 6%

Jumps: 4%

a. Consider a clock length where every instruction completes in one clock cycle, and the clock cycle is the same for all instructions. What is the clock cycle length for this set of instructions?

b. Now consider a variable length clock implementation, where each instruction executes in 1 clock cycle, but the clock cycle length is determined by the instruction. What is its average clock cycle length?

c. Find the performance ratio of the variable clock to the single clock.