Using the provided PMOS input deck $($ProjectBase$.$in$)$:

A$.$ Simulate the PMOS device, show its I$-$V plot, and find its threshold voltage $($Vth$).$

B$.$ Modify the code to create a conventional NMOS device for channel length $\backslash ((\backslash$mathrm$\{$Lg$\})\backslash )$ that is assigned to your team, use appropriate materials, and doping.

C$.$ Generate Id$-$Vg characteristics for Vd $($range $0\mathrm{.}01$ V to $1\mathrm{.}0$ V $).$

D$.$ Use the generated transfer function to extract the threshold voltage, Vth $($V$),$ and subthreshold slope S $(\backslash (\backslash$mathrm$\{$mV$\}/\backslash$mathrm$\{$dec$\})\backslash ).$

E$.$ Now by knowing Vth you can generate output characteristics $(\backslash (\backslash$mathrm$\{$Id$\}-\backslash$mathrm$\{$Vd$\}\backslash ))$ for various Vg $,$ see the following hint.

Note: After you know Vth$,$ generate the device characteristics for

$\backslash (\backslash$mathrm$\{$Vg$\}=\backslash$mathrm$\{$V$\}\backslash )$ th and varying Vd from $0\mathrm{.}01$ to $1$ V

$\backslash (\backslash$mathrm$\{$Vg$\}=\backslash$mathrm$\{$Vth$\}+0\mathrm{.}2\backslash )$ and varying Vd from $0\mathrm{.}01$ to $1$ V

$\backslash (\backslash$mathrm$\{$Vg$\}=\backslash$mathrm$\{$Vth$\}+0\mathrm{.}4\backslash )$ and varying Vd from $0\mathrm{.}01$ to $1$ V

$\backslash (\backslash$mathrm$\{$Vg$\}=\backslash$mathrm$\{$Vth$\}+0\mathrm{.}6\backslash )$ and varying Vd from $0\mathrm{.}01$ to $1$ V

F$.($Extra credit, optional$)$ Repeat A through C for various Channel lengths $(\backslash (\backslash$mathrm$\{$Lg$\}=28\backslash$mathrm$\{$~nm$\}\backslash ),\backslash (42\backslash$mathrm$\{$~nm$\},65\backslash$mathrm$\{$~nm$\},90\backslash$mathrm$\{$~nm$\}\backslash ),$ and $120$nm$).$ Find their corresponding Vth and plot the threshold voltages vs$.$ channel length. What do you see?

Submit:

$-$ I$-$V characteristic curve and threshold voltage for original PMOS device.

$-$ Overlaying characteristics curves for your NMOS $($see above note$),$ graphs

$-$ NMOS device mesh structure, figure $-$ NMOS device doping concentration, figure

$-$ Values for threshold voltage, Vth $($V$),$ and sub$-$threshold slope, S$,($mV$/$dec$)$

$-$ Source and drain sheet resistance

$-($optional$)$ Vth versus Channel length plot

Expected NMOS structure after modification: